soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的，含蓄的

牛津词典

adj.

• 软性色情的；（性描写等）隐晦的，含蓄的
  showing or describing sexual activity without being too detailed or shocking

柯林斯词典

• (性描写)非赤裸裸的，较隐晦的
  Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

双语例句

• NIOS ⅱ soft-core processor is a flexible and efficient embedded processor promoted by Altera Corporation.
  NIOSⅡ软核处理器是Altera公司推出的一款灵活高效的嵌入式处理器。
• This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU.
  提出了一种基于FPGA（现场可编程门阵列）和软核CPU的嵌入式系统设计的新方法。
• Implementing the synchronization of industrial Ethernet precise clock based on Nios II soft-core
  基于NiosⅡ软核的工业以太网精确时钟同步的实现
• The paper built a soft core processor which named NIOS II in the FPGA by using SOPC technology, and running μ C/ OS-ⅱ operating system on the NIOS II soft-core in order to achieve the scheduling of the system task.
  通过使用SOPC技术，在FPGA内部构建了NIOSⅡ软核处理器，并在NIOSⅡ软核上运行μC/OS-Ⅱ操作系统，从而实现了对系统任务的调度。
• According to the structure model of data acquisition and processing system connected by Ethernet, the network interface module based on the Nios soft-core system is designed to construct the network data acquisition system.
  为构建网络化的数据采集系统，根据数据采集模块与处理控制模块通过以太网相连接的结构模型，设计了基于Nios软核系统的嵌入式以太网网络接口模块。
• Then, through the embedded soft-core processor technology based on FPGA, entire system the control, and processing and transmission of data of were achieved by using the co-design approach of hardware and software.
  然后，通过基于FPGA的嵌入式软核处理器技术，采用软硬件协同设计的方法，实现对整个系统功能的控制及数据的处理与发送。
• Implementation of Soft-Core Processor and DDFS Based on FPGA
  基于FPGA的软核处理器及DDFS实现
• Design of an Ethernet Interface Based on the Nios Soft-core Processor
  基于Nios软核处理器的以太网接口设计
• Design and Implementation of Multi-channel Phone-billing-system Based upon NIOS Soft-core CPU
  基于NIOS软核CPU技术的多路电话计费系统的设计与实现
• Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
  详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。