soft-core

英 [ˈsɒft kɔː(r)]

美 [ˈsɔːft kɔːr]

adj.  软性色情的; (性描写等)隐晦的，含蓄的

牛津词典

adj.

• 软性色情的；（性描写等）隐晦的，含蓄的
  showing or describing sexual activity without being too detailed or shocking

柯林斯词典

• (性描写)非赤裸裸的，较隐晦的
  Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.

双语例句

• To solute the problem, the idea of kernel hardware design has been put forward. System architecture is divided into soft-core and hardcore. Hardcore will manage application tasks as a coprocessor to improve the real time of system.
  针对实时性问题，提出将内核硬件化设计的思想，将系统的体系结构划分为软核和硬核，硬核作为协处理器管理应用任务，提高系统的实时性，使系统的性能得到明显的提高。
• The paper built a soft core processor which named NIOS II in the FPGA by using SOPC technology, and running μ C/ OS-ⅱ operating system on the NIOS II soft-core in order to achieve the scheduling of the system task.
  通过使用SOPC技术，在FPGA内部构建了NIOSⅡ软核处理器，并在NIOSⅡ软核上运行μC/OS-Ⅱ操作系统，从而实现了对系统任务的调度。
• NIOS ⅱ soft-core processor is a flexible and efficient embedded processor promoted by Altera Corporation.
  NIOSⅡ软核处理器是Altera公司推出的一款灵活高效的嵌入式处理器。
• The Nios ⅱ soft-core processor improve the integration of the system and is helpful to the miniaturization of instrument.
  NiosⅡ软核处理器提高了系统的集成度，有利于系统的小型化，降低了成本。
• The prototype designs with soft-core processors of Nios II in FPGA, improves the programmability of network processors.
  网络处理器芯片原型采用NIOSii软核处理器在FPGA上实现，提高了网络处理器的可编程能力。
• SOPC includes soft-core or hard-core CPU 、 memory 、 I/ O and programmable logic resource, which has all the advantage of SOC 、 PLD and FPGA.
  SOPC综合了SOC、PLD和FPGA的优点，集成了硬核或软核CPU、存储器、I/O以及可编程逻辑。
• This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU.
  提出了一种基于FPGA（现场可编程门阵列）和软核CPU的嵌入式系统设计的新方法。
• Nios II soft-core processor implanted into FPGA as the control chip controls and preprocesses the data of the entire image acquisition system.
  采用FPGA作为控制芯片，在其中植入NiosⅡ软核处理器以对整个图像采集系统的数据进行控制和预处理。
• With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
  通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。
• Research and Design of Soft-core IP for AVS Inter Decoder
  AVS帧间解码IP软核的研究与设计